Method of manufacturing a semiconductor integrated circuit device

ABSTRACT

A protection film is formed on a silicon oxide film  6  formed on the surface of a semiconductor substrate, a silicon oxide film is removed from a region where a thin gate-insulating film is to be formed by using, as a mask, a photoresist pattern that covers a region where a thick gate-insulating film is to be formed, and, then, the photoresist pattern is removed followed by washing. Then, the semiconductor substrate is heat-oxidized or a film is deposited thereon to form gate-insulating films having different thicknesses.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method of manufacturing asemiconductor integrated circuit device. More particularly, theinvention relates to technology that can be effectively adapted to asemiconductor integrated circuit device containing two kinds of MISFETs(metal insulator semiconductor field-effect transistors) to whichdifferent voltages are applied.

[0003] 2. Prior Art

[0004] In a memory LSI such as CMOS (complementary metal oxidesemiconductor) logic LSI (large scale integrated circuit) and SRAM(static random access memory) or DRAM (dynamic random access memory) andin a CMOS logic LSI mounting a memory circuit, the power source voltagesmay not often be the same between the internal circuit and theinput/output circuit. In the CMOS logic LSI, for example, the length(gate length) of the gate electrodes of MISFETs in the internal circuitis set to be shorter than the gate length of MISFETs in the input/outputcircuit in order to increase the speed. In order to maintain a breakdownvoltage of the semiconductor regions constituting the sources and drainsof MISFETs in the internal circuit, however, the power-source voltagefor the internal circuit is set to be lower than the power-sourcevoltage for the input/output circuit. Here, in order to maintainreliability of the gate-insulating films of MISFETs in the input/outputcircuit having the high power-source voltage, the thickness of thegate-insulating films is selected to be larger than the thickness of thegate-insulating films of MISFETs in the internal circuit having the lowpower-source voltage.

[0005] Two kinds of gate-insulating films having different thicknessesare formed on a semiconductor substrate of silicon by, first, formingelement isolation regions on the main surface of the semiconductorsubstrate and, then, subjecting the semiconductor substrate to the heatoxidation treatment of the first time to form a silicon oxide film onthe surface of the semiconductor substrate. Next, active regions wherethe thick gate-insulating film will be formed are covered with aphotoresist film, the silicon oxide film on the active regions on wherethe thin gate-insulating film will be formed is removed by wet etchingand, then, the photoresist film is removed, followed heat-oxidizing thesemiconductor substrate in the second time. That is, the thingate-insulating film is formed through the heat oxidation of the secondtime, and the thick gate-insulating film is formed through the heatoxidation of the first time and through the heat oxidation of the secondtime.

SUMMARY OF THE INVENTION

[0006] Through their study, however, the present inventors havediscovered the fact that according to the above-mentioned method offorming two kinds of gate-insulating films of different thicknesses, theactive regions on where the thick gate-insulating film is to be formedis covered with the photoresist film at the time of removing, by wetetching, the silicon oxide film from the active regions on where thethin gate-insulating film is to be formed. Therefore, the thingate-insulating film, thick gate-insulating film or these twogate-insulating films lose breakdown voltage due to contamination causedby the photoresist film and due to any damage in the step of removingthe photoresist film and in the subsequent step of washing.

[0007] The object of the present invention is to provide technologycapable of improving reliability of the semiconductor integrated circuitdevice containing a plurality of kinds of MISFETs having gate-insulatingfilms of different thicknesses.

[0008] The above and other objects as well as novel features of theinvention will become obvious from the description of the specificationand the accompanying drawings.

[0009] Briefly described below are representative examples of theinvention disclosed in this application.

[0010] That is, the invention is concerned with a process for formingtwo kinds of gate-insulating films, wherein a first insulating film isformed by etching, using a photoresist film as a mask, on a region of asemiconductor substrate on where an insulating film of a firstrelatively large thickness is to be formed and, then, a secondinsulating film is formed on the first insulating film in order toprevent the first insulating film from being scraped off in the step ofwashing which precedes the processing for forming an insulating film ofa second relatively small thickness.

[0011] Further, the invention is concerned with a process for formingtwo kinds of gate-insulating films, wherein a first insulating film isformed by etching, using a photoresist film as a mask, on a region of asemiconductor substrate on where an insulating film of a firstrelatively large thickness is to be formed and, then, a secondinsulating film that has been formed in advance on the first insulatingfilm is used as an etching stopper in the step of washing which precedesthe processing for forming an insulating film of a second relativelysmall thickness.

[0012] Other representative examples of the invention disclosed in theapplication are as described below briefly.

[0013] 1. A method of manufacturing a semiconductor integrated circuitdevice by forming an insulating film of a first thickness on a firstactive region of a semiconductor substrate and forming an insulatingfilm of a second thickness smaller than said first thickness on a secondactive region, said method comprising the steps of:

[0014] (a) forming a first insulating film on the surface of saidsemiconductor substrate;

[0015] (b) forming a second insulating film which is a protection filmon said first insulating film;

[0016] (c) covering said first active region with a masking pattern;

[0017] (d) successively removing said second insulating film and saidfirst insulating film from said second active region by using saidmasking pattern as a mask;

[0018] (e) selectively removing chiefly said second insulating film fromsaid first active region after said masking pattern has been removed;and

[0019] (f) forming a third insulating film on said semiconductorsubstrate.

[0020] 2. A method of manufacturing a semiconductor integrated circuitdevice by forming an insulating film of a first thickness on a firstactive region of a semiconductor substrate and forming an insulatingfilm of a second thickness smaller than said first thickness on a secondactive region, said method comprising the steps of:

[0021] (a) forming a first insulating film on the surface of saidsemiconductor substrate;

[0022] (b) forming a second insulating film which is a protection filmon said first insulating film after the surface of said first insulatingfilm has been removed by not more than about 1 nm;

[0023] (c) covering said first active region with a masking pattern;

[0024] (d) successively removing said second insulating film and saidfirst insulating film from said second active region by using saidmasking pattern as a mask;

[0025] (e) selectively removing said second insulating film from saidfirst active region after said masking pattern has been removed; and

[0026] (f) forming a third insulating film on said semiconductorsubstrate.

[0027] 3. A method of manufacturing a semiconductor integrated circuitdevice, comprising the steps of:

[0028] (a) forming a first insulating film on the surface, of asemiconductor substrate;

[0029] (b) forming a second insulating film which is a protection filmon said first insulating film;

[0030] (c) forming a masking pattern on said semiconductor substrate soas to cover a first region on where an insulating film having arelatively large thickness will be formed but not covering a secondregion on where an insulating film having a relatively small thicknesswill be formed other than said first region;

[0031] (d) successively removing said second insulating film and saidfirst insulating film from said second active region by using saidmasking pattern as a mask;

[0032] (e) after said masking pattern has been removed, removing saidsecond insulating film by washing said semiconductor substrate, saidsecond insulating film being used for suppressing said first insulatingfilm from being scraped off; and

[0033] (f) forming a third insulating film on said semiconductorsubstrate in order to form an insulating film of a first relativelylarge thickness on said first region and to form an insulating film of asecond relatively small thickness on said second region.

[0034] 4. A method of manufacturing a semiconductor integrated circuitdevice according to 1, 2 or 3 above, wherein the heat-nitriding iseffected after

[0035] (a) the step of forming the first insulating film or after (f)the step of forming the third insulating film.

[0036] 5. A method of manufacturing a semiconductor integrated circuitdevice according to 1, 2 or 3 above, wherein the plasma-nitriding or theradical-nitriding is effected after (a) the step of forming the firstinsulating film or after (f) the step of forming the third insulatingfilm.

[0037] 6. A method of manufacturing a semiconductor integrated circuitdevice according to 4 or 5 above, further comprising a step of forming apolycrystalline silicon film containing boron on said third insulatingfilm.

[0038] 7. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 6 above, wherein after chiefly saidsecond insulating film only has been removed in said step (d),impurities for controlling the threshold voltage are injected throughsaid first insulating film.

[0039] 8. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 7 above, wherein the rate of etchingsaid second insulating film is larger than the rate of etching saidfirst insulating film in said step (e).

[0040] 9. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 8 above, wherein the amount ofreduction of the thickness of said first insulating film in said step(e) is not more than 1 nm.

[0041] 10. A method of manufacturing a semiconductor integrated circuitdevice, comprising the steps of:

[0042] (a) forming a first insulating film on the surface of asemiconductor substrate having a first active region and a second activeregion;

[0043] (b) forming a second insulating film which is a protection filmon said first insulating film;

[0044] (c) successively removing said second insulating film and saidfirst insulating film from said second active region;

[0045] (d) washing said semiconductor substrate after said step (c);

[0046] (e) forming a third insulating film on said semiconductorsubstrate after said step (d) to form an insulating film of a firstrelatively large thickness on said first active region and to form aninsulating film of a second relatively small thickness on said secondactivate region;

[0047] wherein in effecting the washing in said step (d), the rate foretching said second insulating film is larger than the rate for etchingsaid first insulating film, and said second insulating film is removedfrom said second active region.

[0048] 11. A method of manufacturing a semiconductor integrated circuitdevice according to 10 above, wherein the amount of reduction of thethickness of said first insulating film in said step (d) is not morethan 1 nm.

[0049] 12. A method of manufacturing a semiconductor integrated circuitdevice according to 9 or 11 above, wherein the amount of reduction ofthe thickness of said first insulating film in said step (d) is from 0.2to 0.4 nm.

[0050] 13. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 12 above, wherein said secondinsulating film is formed by the chemical vapor-phase deposition method.

[0051] 14. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 13 above, wherein said firstinsulating film is formed by the heat oxidation method, and said secondinsulating film is formed by the chemical vapor-phase deposition method.

[0052] 15. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 14 above, wherein said firstinsulating film and said second insulating film are silicon oxide films.

[0053] 16. A method of manufacturing a semiconductor integrated circuitdevice, comprising the steps of:

[0054] (a) forming a first insulating film on the surface of asemiconductor substrate;

[0055] (b) forming a second insulating film which is a protection filmon said first insulating film;

[0056] (c) forming a masking pattern on said semiconductor substrate soas to cover a first region on where an insulating film having arelatively large thickness, will be formed but not covering a secondregion on where an insulating film having a relatively small thicknesswill be formed other than said first region;

[0057] (d) successively removing said second insulating film and saidfirst insulating film from said second active region by using saidmasking pattern as a mask;

[0058] (e) after said masking pattern has been removed, washing saidsemiconductor substrate using said second insulating film as a stopper;and

[0059] (f) forming a third insulating film on said semiconductorsubstrate in order to form an insulating film of a first relativelylarge thickness on said first region and to form an insulating film of asecond relatively small thickness on said second region.

[0060] 17. A method of manufacturing a semiconductor integrated circuitdevice according to 16 above, wherein the rate of etching said secondinsulating film is smaller than the rate of etching said firstinsulating film in said step (e).

[0061] 18. A method of manufacturing a semiconductor integrated circuitdevice according to 16 or 17 above, wherein said second insulating filmhas anti-oxidizing property.

[0062] 19. A method of manufacturing a semiconductor integrated circuitdevice according to 16, 17 or 18 above, wherein after said firstinsulating film has been formed, said said second insulating film isformed on said semiconductor substrate by the chemical vapor-phasedeposition method.

[0063] 20. A method of manufacturing a semiconductor integrated circuitdevice according to 16, 17 or 18 above, wherein after said firstinsulating film has been formed, said second insulating film is formedon said semiconductor substrate by the heat-nitriding.

[0064] 21. A method of manufacturing a semiconductor integrated circuitdevice according to 16, 17 or 18 above, wherein after said firstinsulating film has been formed, said second insulating film is formedon said semiconductor substrate by the plasma-nitriding or theradical-nitriding.

[0065] 22. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 16 to 21 above, wherein said secondinsulating film comprises silicon nitride.

[0066] 23. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 20 to 22 above, further comprising a stepof forming a polycrystalline silicon film containing boron on said thirdinsulating film.

[0067] 24. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 16 to 23 above, wherein saidsemiconductor substrate is heat-oxidized in said step (f) in a statewhere said first region is suppressed by said second insulating filmfrom being oxidized, thereby to form said third insulating film on thesemiconductor substrate of said second region.

[0068] 25. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 21 above, wherein said thirdinsulating film is formed on the semiconductor substrate by the chemicalvapor-phase deposition method in said step (f).

[0069] 26. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 25 above, wherein said thirdinsulating film is composed of a material having a dielectric constantlarger than that of said first insulating film.

[0070] 27. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 26 above, wherein at least a portionof said third insulating film comprises tantalum oxide, titanium oxideor silicon nitride.

[0071] 28. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 13 or 16 to 24 above, wherein saidfirst insulating film is formed by the chemical vapor-phase depositionmethod.

[0072] 29. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 16 to 24 or 28 above, wherein said firstinsulating film comprises silicon oxide.

[0073] 30. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 29 above, wherein the insulatingfilm having said first thickness and the insulating film having saidsecond thickness are the gate-insulating films of the MIS transistors.

[0074] 31. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 30 above, further comprising thesteps of:

[0075] (a) depositing an electrically conducting film for forming thegate electrode on the semiconductor substrate after the insulating filmof said first thickness and the insulating film of said second thicknesshave been formed;

[0076] (b) forming the gate electrodes by patterning the electricallyconducting film for forming said gate electrodes; and

[0077] (c) introducing impurities into said semiconductor substrate toform a pair of semiconductor regions for forming source and drain.

[0078] 32. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 31 above, further comprising thesteps of:

[0079] (a) depositing an electrically conducting film for forming thegate electrode on the semiconductor substrate after the insulating filmof said first thickness and the insulating film of said second thicknesshave been formed;

[0080] (b) forming a masking film on the electrically conducting filmfor forming said gate electrodes permitting the first element region tobe exposed but covering the second element region, and introducing firsttype of impurities into the electrically conducting film for formingsaid gate electrodes using said masking film as a mask;

[0081] (c) forming a masking film on the electrically conducting filmfor forming said gate electrodes permitting said second element regionto be exposed but covering said first element region, and introducingsecond type of impurities having a type of electric conduction differentfrom said first type of impurities into the electrically conducting filmfor forming said gate electrodes using said masking film as a mask; and

[0082] (d) forming the gate electrodes of a first type of electricconduction containing said first type of impurities by patterning theelectrically conducting film for forming said gate electrodes, andforming the gate electrodes of a second type of electric conductioncontaining said second type of impurities.

[0083] 33. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 32 above, further comprising thesteps of:

[0084] (a) depositing an electrically conducting film for forming thegate electrode on the semiconductor substrate after the insulating filmof said first thickness and the insulating film of said second thicknesshave been formed;

[0085] (b) forming a masking film on the electrically conducting filmfor forming said gate electrodes permitting the first element region tobe exposed but covering the second element region, and introducing firsttype of impurities into the electrically conducting film for formingsaid gate electrodes using said masking film as a mask;

[0086] (c) forming a masking film on the electrically conducting filmfor forming said gate electrodes permitting said second element regionto be exposed but covering said first element region, and introducingsecond type of impurities having a type of electric conduction differentfrom said first type of impurities into the electrically conducting filmfor forming said gate electrodes using said masking film as a mask;

[0087] (d) depositing a third electrically conducting film for forminggate electrodes on the electrically conducting film for forming saidgate electrodes via the second electrically conducting film for formingthe gate electrodes; and

[0088] (e) patterning said first, second and third electricallyconducting films for forming said gate electrodes in order to form thegate electrodes of a first type of electric conduction using said firstelectrically conducting film containing said first type of impuritiesand to form the gate electrodes of a second type of electric conductionusing said first electrically conducting film containing said secondtype of impurities.

[0089] 34. A method of manufacturing a semiconductor integrated circuitdevice according to 33 above, wherein said first electrically conductingfilm is polycrystalline silicon, said second electrically conductingfilm is tungsten nitride or titanium nitride, and said thirdelectrically conducting film is tungsten.

[0090] 35. A method of manufacturing a semiconductor integrated circuitdevice according to any one of 1 to 32 above, further comprising thesteps of:

[0091] (a) depositing an electrically conducting film for forming thegate electrode on the semiconductor substrate after the insulating filmof said first thickness and the insulating film of said second thicknesshave been formed;

[0092] (b) patterning the electrically conducting film for forming saidgate electrodes to form the gate electrodes;

[0093] (c) introducing impurities into said semiconductor substrate toform a pair of semiconductor regions for forming source and drain;

[0094] (d) forming side wall-insulating films on the side surfaces ofsaid gate electrodes;

[0095] (e) depositing an electrically conducting film for formingsilicide on said semiconductor substrate in a state where the uppersurfaces of said gate electrodes and part or whole of the pair ofsemiconductor regions are exposed; and

[0096] (f) heat-treating said semiconductor substrate to form a silicidelayer in a contact portion between the electrically conducting film forforming said silicide and the gate electrodes or the pair ofsemiconductor regions.

[0097] In forming a plurality of kinds of gate insulating films havingdifferent thicknesses according to the above-mentioned means, thephotoresist pattern is not directly formed on the first insulating filmthat constitutes a relatively thick gate-insulating film but, instead,the photoresist pattern is formed via the second insulating film or viaa reformed layer of the first insulating film. Therefore, contaminantsfrom the photoresist film adhere on the second insulating film or on thereformed layer of the first insulating film. As the first insulatingfilm, there is used a film formed by heat-treating the semiconductorsubstrate, a film formed by the chemical vapor-phase deposition method,or a film formed by nitriding the film that has been formed by thechemical vapor-phase deposition method. As the second insulating film,there is used a film formed by, for example, the chemical vapor-phasedeposition method which is different from the method of forming thefirst insulating film. This enables the second insulating film in thewashing solution to be etched at a rate larger than the rate of etchingthe first insulating film. By selectively removing the second insulatingfilm by utilizing the difference in the etching rate, therefore, thefirst insulating film is not affected by the contamination caused theresist and, besides, damage to the first insulating film can be avoidedin the step of removing the resist and in the subsequent washing step.By removing the surface portion of the first insulating film within sucha degree that no defect develops in the film, further, it is allowed toremove contaminants adhered on the interface between the firstinsulating film and the second insulating film, contributing to furtherimproving reliability of the gate-insulating film.

[0098] According to the above means, further, in effecting the washingprior to forming the insulating film of the relatively small secondthickness, the second insulating film prevents the first insulating filmfrom being scraped off on the region on where the insulating film of therelatively large first thickness is formed, so that weak spots in thefirst insulating film will not be exposed and that fine pores will notbe formed. Therefore, the gate-insulating film having the relativelylarge first thickness is suppressed or prevented from losing breakdownvoltage, and the quality of the gate-insulating film can be improved.

[0099] According to the above means, further, in effecting the washingprior to forming the insulating film of the relatively small secondthickness, the second insulating film formed in advance on the firstinsulating film on the region on where the insulating film of therelatively large first thickness has been formed, works as an etchingstopper so that the first insulating film is not scraped off, weak spotsin the first insulating film will not be exposed and that fine poreswill not be formed. Therefore, the gate-insulating film having therelatively large first thickness is prevented from losing the breakdownvoltage that stems when the first insulating film is scraped off duringthe washing, and improved quality of the gate-insulating film can bemaintained.

BRIEF DESCRIPTION OF THE DRAWINGS

[0100] FIGS. 1(a) to 1(d) are sectional views illustrating a majorportion of a semiconductor substrate in the steps of manufacturing asemiconductor integrated circuit device according to a technical idea ofthe invention;

[0101] FIGS. 2(a) and 2(b) are graphs showing the measured results ofbreakdown voltages of a silicon oxide film 9 a based on a process forforming two kinds of gate-insulating films according to the technicalidea of the invention;

[0102] FIGS. 3(a) to 3(d) are graphs comparing the measured results ofbreakdown voltage of a silicon oxide film 52 based on the process forforming two, kinds of gate-insulating films studied by the inventors;

[0103] FIGS. 4(a) and 4(b) are graphs comparing the measured results ofbreakdown voltage of the silicon oxide film formed by a process forforming one kind of gate-insulating film;

[0104]FIG. 5 is a diagram drawing the experimental results conducted bythe present inventors, and shows a relationship between the etchingamount (equivalent to washing time) in the direction of thickness of thesilicon oxide film on the thin-film portion after the washing and thethickness of the silicon oxide film remaining on the semiconductorsubstrate;

[0105]FIG. 6 is a graph showing the measured results of a relationship(I-V characteristics) between the gate current and the gate voltageaccording to the technical idea of the invention;

[0106]FIG. 7 is a graph corresponding to FIG. 6 and shows the measuredresults of a relationship (I-V characteristics) between the gate currentand the gate voltage according to technology studied by the presentinventors;

[0107]FIG. 8 is a graph illustrating a relationship between the defectdensity and the etched amount of the silicon oxide film on thethick-film portion through the pre-washing;

[0108]FIG. 9 is a graph showing a relationship between the defectdensity and the breakdown electric field intensity of the silicon oxidefilm on the side of the thin-film portion of when the silicon oxide filmon the thin-film portion is scraped off by about 1 nm through thepre-washing, and wherein FIG. 9(a) shows a case of when there isemployed a process for forming one kind of gate-insulating film, andFIG. 9(b) shows a case of when there is employed a process for formingtwo kinds of gate-insulating films according to the technical idea ofthe invention;

[0109] FIGS. 10(a) and 10(b) are graphs showing the measured results ofbreakdown voltage of the silicon oxide film constituting thegate-insulating film on the thick-film portion of when the technicalidea of the invention is adapted to the salicide process;

[0110] FIGS. 11(a) and 11(b) are graphs showing the measured results ofbreakdown voltage of the silicon oxide film constituting thegate-insulating film on the thick-film portion of when the process forforming two kinds of gate-insulating films studied by the presentinventors is adapted to the salicide process;

[0111]FIG. 12 is a graph showing a relationship between the stressingtime (time until failure occurs) and the cumulative failure for everyscrape-off of the silicon oxide film on the thick-film portion throughthe pre-washing;

[0112]FIG. 13 is a graph illustrating the dependance of the final filmthickness on the thickness of the remaining silicon oxide film of whenthe semiconductor substrate is oxidized in a state where the siliconoxide film is still remaining on the thick-film portion after thepre-washing;

[0113]FIG. 14 is a sectional view of a major portion of thesemiconductor substrate illustrating a method of manufacturing a CMOSdevice according to an embodiment of the invention;

[0114]FIG. 15 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0115]FIG. 16 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0116]FIG. 17 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0117]FIG. 18 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0118]FIG. 19 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0119]FIG. 20 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0120]FIG. 21 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0121]FIG. 22 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0122]FIG. 23 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0123]FIG. 24 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0124]FIG. 25 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0125]FIG. 26 is a sectional view of a major portion of thesemiconductor substrate illustrating the method of manufacturing theCMOS device according to the embodiment of the invention;

[0126]FIG. 27 is a graph illustrating the evaluated results of breakdownvoltage of the silicon oxide film constituting a thick gate-insulatingfilm to which the embodiment 1 is applied;

[0127]FIG. 28 is a graph illustrating a relationship between thethickness of the silicon oxide film constituting the thickgate-insulating film and the thickness of the silicon oxide film formedby the CVD method, the silicon oxide film formed by the CVD methodcontacting to the photoresist film, according to the embodiment 1;

[0128]FIG. 29 is a plan view of a semiconductor chip constitutinganother semiconductor integrated circuit device according to theembodiment 1;

[0129]FIG. 30 is a sectional view of a major portion of a semiconductorsubstrate illustrating the method of forming a gate-insulating film ofan MISFET according to another embodiment of the invention;

[0130]FIG. 31 is a sectional view of the major portion of thesemiconductor substrate illustrating the method of forming thegate-insulating film of the MISFET according to another embodiment ofthe invention;

[0131]FIG. 32 is a sectional view of the major portion of thesemiconductor substrate illustrating the method of forming thegate-insulating film of the MISFET according to another embodiment ofthe invention;

[0132]FIG. 33 is a sectional view of the major portion of thesemiconductor substrate illustrating the method of forming thegate-insulating film of the MISFET according to another embodiment ofthe invention;

[0133]FIG. 34 is a view illustrating a film-forming device used inanother embodiment of the invention;

[0134]FIG. 35 is a diagram illustrating the distribution of thecontained element in the direction of thickness of the insulating filmformed by the film-forming device of FIG. 34;

[0135]FIG. 36 is a diagram illustrating the distribution of thecontained element in the direction of thickness of the insulating filmformed by the heat-nitriding;

[0136]FIG. 37 is a sectional view of a major portion of a semiconductorsubstrate illustrating the method of forming a gate-insulating film ofan MISFET according to a further embodiment of the invention;

[0137]FIG. 38 is a sectional view of the major portion of thesemiconductor substrate illustrating the method of forming thegate-insulating film of the MISFET according to a further embodiment ofthe invention;

[0138]FIG. 39 is a sectional view of the major portion of thesemiconductor substrate illustrating the method of forming thegate-insulating film of the MISFET according to a further embodiment ofthe invention;

[0139]FIG. 40 is a sectional view of the major portion of thesemiconductor substrate illustrating the method of forming thegate-insulating film of the MISFET according to a further embodiment ofthe invention;

[0140]FIG. 41 is a sectional view of the major portion of thesemiconductor substrate illustrating, the method of forming thegate-insulating film of the MISFET according to a further embodiment ofthe invention;

[0141]FIG. 42 is a sectional view of the major portion of thesemiconductor substrate illustrating the method of forming thegate-insulating film of the MISFET according to a further embodiment ofthe invention;

[0142]FIG. 43 is a sectional view of the major portion of thesemiconductor substrate illustrating the method of forming thegate-insulating film of the MISFET according to a further embodiment ofthe invention;

[0143]FIG. 44 is a sectional view of the major portion of thesemiconductor substrate illustrating the method of forming thegate-insulating film of the MISFET according to a further embodiment ofthe invention;

[0144] FIGS. 45(a) to 45(d) are sectional views of a major portion of asemiconductor substrate in the steps for manufacturing a semiconductorintegrated circuit device for explaining a further technical idea of theinvention;

[0145]FIG. 46 is a sectional view of a major portion of thesemiconductor substrate in a step of manufacturing the semiconductorintegrated circuit device according to a further embodiment of theinvention;

[0146]FIG. 47 is a sectional view of the major portion of thesemiconductor substrate in a step of manufacturing the semiconductorintegrated circuit device following FIG. 46;

[0147]FIG. 48 is a sectional view of the major portion of thesemiconductor substrate in a step of manufacturing the semiconductorintegrated circuit device following FIG. 47;

[0148]FIG. 49 is a sectional view of the major portion of thesemiconductor substrate in a step of manufacturing the semiconductorintegrated circuit device following FIG. 48;

[0149]FIG. 50 is a sectional view of the major portion of thesemiconductor substrate in a step of manufacturing the semiconductorintegrated circuit device following FIG. 49;

[0150]FIG. 51 is a sectional view of a major portion of a semiconductorsubstrate in a step of manufacturing a semiconductor integrated circuitdevice according to a still further embodiment of the invention;

[0151]FIG. 52 is a sectional view of the major portion of thesemiconductor substrate in a step of manufacturing the semiconductorintegrated circuit device following FIG. 51;

[0152]FIG. 53 is a sectional view of a major portion of thesemiconductor substrate in a step of manufacturing a semiconductorintegrated circuit device according to a yet further embodiment of theinvention;

[0153]FIG. 54 is a sectional view of the major portion of thesemiconductor substrate in a step of manufacturing the semiconductorintegrated circuit device following FIG. 53;

[0154]FIG. 55 is a sectional view of the major portion of thesemiconductor substrate in a step of manufacturing the semiconductorintegrated circuit device following FIG. 54;

[0155]FIG. 56 is a sectional view of the major portion of thesemiconductor substrate in a step of manufacturing the semiconductorintegrated circuit device following FIG. 55;

[0156]FIG. 57 is a sectional view of the major portion of thesemiconductor substrate in a step of manufacturing the semiconductorintegrated circuit device following FIG. 56; and

[0157] FIGS. 58(a) to 58(d) are sectional views of a major portion of asemiconductor substrate in a process for forming two kinds ofgate-insulating films studied by the present inventors for embodying theinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0158] Embodiments of the present invention will now be described indetail with reference to the drawings.

[0159] In all drawings explaining the embodiments, the portions havingthe same functions are denoted by the same reference numerals but theirdescription is not repeated.

Embodiment 1

[0160] Prior to describing the embodiment 1, mentioned below are aprocess for forming two kinds of gate-insulating films and theassignment therefor discussed by the present inventors for accomplishingthe invention. In the drawings, the left side is a region (thin-filmportion) IR forming an MISFET having a thin gate-insulating film and theright side is a region (thick-film portion) CR forming a MISFET havingan thick gate-insulating film.

[0161]FIG. 58(a) is a partial sectional view of a semiconductorsubstrate 50 in a step of manufacture. First, a groove is formed in thesemiconductor substrate 50, an insulating film of silicon oxide or thelike is buried in the groove, and a groove-type isolation portion 51 isformed on the main surface of the semiconductor substrate 50. Then, thesemiconductor substrate 50 is heat-oxidized to form a first siliconoxide film 52 on the main surface (active region) of the semiconductorsubstrate 50, a photoresist film 53 is formed in a manner of directlycontacted onto the silicon oxide film 52 so as to cover the thick-filmportion CK but permitting the thin-film portion to be exposed, and thefirst silicon oxide film 52 is removed from the thin-film portion IRusing the photoresist film 53 as an etching mask.

[0162] Then, the photoresist film 53 is removed by ashing to obtain asectional structure shown in FIG. 58(b). Then, the washing is effected.The washing includes, for example, a first washing treatment (SC1) and asecond washing treatment (SC2). The first washing treatment (SC1) ischiefly for removing foreign matter and, for example, NH₃/H₂O₂ is usedas a washing solution. The second washing treatment (SC2) is chiefly forremoving metals and, for example, HCl/H₂O₂ is used as a washingsolution.

[0163] Thereafter, the whole semiconductor substrate 50 inclusive of themain surface is pre-washed. The pre-washing is an important treatmentfor reducing or eliminating damage at the time of removing thespontaneously oxidized film or the photoresist film formed on the mainsurface of, for example, the thin-film portion on the semiconductorsubstrate 50, and for reducing or eliminating contamination in the firstsilicon oxide film on the thick-film portion CK caused by thephotoresist film. According to the study by the present inventors, itwas discovered that when it is presumed that the silicon oxide filmexists on the thin-film portion IR, the pre-washing is necessary forremoving the silicon oxide film by a thickness of, for example, not lessthan 1 nm and, desirably, by about 2 nm from the standpoint of improvingreliability. According to technology discussed by the present inventors,the first washing and the third washing (DHF) are effected in thepre-washing treatment. The third washing (DHF) is for chiefly removingthe spontaneously oxidized film and, for example, hydrofluoric acid isused as the washing solution. When the pre-washing is effected, theupper portion of the first silicon oxide film 52 on the thick-filmportion CK is scraped off as shown in FIG. 58(c). Symbol Δdox representsthe amount of the silicon oxide film 52 scraped off.

[0164] After the pre-washing, the semiconductor substrate 50 issubjected to a second heat-oxidation treatment thereby to form a secondsilicon oxide film 53 on the thin-film portion of the semiconductorsubstrate 50 as shown in FIG. 58(d) and to form the first silicon oxidefilm 52 on the thick-film portion CK maintaining a thickness larger thanthat of the second silicon oxide film 53 on the thin-film portion IR.Thereafter, gate electrodea are formed on the first and second siliconoxide films in the same manner as that of forming an ordinaryfield-effect transistor.

[0165] In carrying out the above process for forming two kinds ofgate-insulating films, the present inventors have discovered thefollowing assignment based on the experimental results. That is, inconducting the pre-washing, the upper part of the first silicon oxidefilm 52 is scraped off, weak spots considered to be existing in thefirst silicon oxide film 52 are exposed and are further expanded to formvery fine pores. When the gate electrode is formed on the first siliconoxide film 52 that has been completed, the fine pores are furtherexpanded due to stress produced by the gate electrode. Then, the qualityof the first silicon oxide film 52 that requires a high breakdownvoltage is deteriorated, and the breakdown voltage is no longermaintained.

[0166] In this invention, therefore, another insulating film isinterposed between the silicon oxide film on the thick-film portion CKthat requires the large breakdown voltage and the photoresist film forpatterning the silicon oxide film in the process for forming two kindsof gate-insulating films. This makes it possible to greatly decrease thescraping amount of the silicon oxide film on the thick-film portion CKduring the pre-washing. Accordingly, weak spots considered to beexisting in the silicon oxide film on the thick-film portion CK aresuppressed or preventing from being exposed. Further, since thephotoresist film does not come into direct contact with the siliconoxide film on the thick-film portion CK, the silicon oxide film on thethick-film portion CK is little contaminated or is not contaminated bythe photoresist film. Moreover, another insulating film is formed on thesilicon oxide film on the thick-film portion CK under the photoresistfilm. At the time of removing the photoresist film, therefore, theunderlying film (silicon oxide film on the thick-film portion) is littledamaged.

[0167] The technical idea of the invention will now be described withreference to FIGS. 1(a) to 1(d) which are sectional views illustrating amajor portion of a semiconductor substrate at the same position.

[0168] Referring, first, to FIG. 1(a), a shallow groove 2 is engraved ina semiconductor substrate 1, and a silicon oxide film 3 or the like filmis buried in the shallow groove 2 to form, for example, a groove-typeelement isolation region (trench isolation) on the main surface of thesemiconductor substrate 1. Then, the semiconductor substrate 1 isheat-oxidized to form a silicon oxide film 6 on the main surface (activeregion) of the semiconductor substrate 1, and a silicon oxide film 7 isformed as a protection film in a manner of being directly contacted tothe silicon oxide film 6 by, for example, the CVD (chemical vapordeposition) method. Then, a photoresist pattern (masking film, maskingpattern) is formed thereon being directly contacted thereto so as tocover the thick-film portion CK but permitting the thin-film portion tobe exposed. By using the photoresist pattern 8 as an etching mask,further, the silicon oxide film 6 and the protection film 7 are removedfrom the thin film portion IR.

[0169] Then, the photoresist pattern 8 is removed by ashing to obtain asectional structure as shown in FIG. 1(b). At this moment, the siliconoxide film 7 which is a protection film has been formed on the siliconoxide film 6 under the photoresist pattern 8, and the silicon oxide film6 is little damaged. The washing treatment is effected. In washing theback surface, the first washing (SC1) and the second washing (SC2) areeffected. The first washing and the second washing are the same as thoseemployed for the process for forming two kinds of gate-insulating filmsdiscussed by the present inventors, and are not described here again.

[0170] Next, the whole semiconductor substrate 1 inclusive of the mainsurface is subjected to the pre-washing (first washing and third washing(DHF)) like in the process for forming two kinds of gate-insulatingfilms discussed by the present inventors. This makes it possible toreduce or eliminate damage at the time of removing the spontaneouslyoxidized film or removing the photoresist film formed on the mainsurface of, for example, the thin-film portion IR of the semiconductorsubstrate 1. According to the technical idea of the invention, thesilicon oxide film 6 on the thick-film portion CK does not come indirect contact with the photoresist pattern 8, and the silicon oxidefilm 6 is little contaminated or is not contaminated by the photoresistfilm. In conducting the pre-washing, therefore, much consideration needsnot be given to the contamination of the silicon oxide film 6 by thephotoresist film.

[0171] Upon effecting the pre-washing, the silicon oxide film 7 can bechiefly removed by etching, since the silicon oxide film 7 which is theprotection film formed the CVD method is etched at a rate larger than arate at which the silicon oxide film 6 formed by the heat-oxidation isetched. In this pre-washing, too, the upper part of the silicon oxidefilm 6 on the thick-film portion CK is scraped off by about Δdox asshown in FIG. 1(c). In this case, however, the scraping amount can besuppressed to be very small so that the weak spots will not be exposed.It is, therefore, made possible to maintain the breakdown voltage of thegate-insulating film on the thick-film portion that requires the largebreakdown voltage.

[0172] After the pre-washing, the semiconductor substrate 1 is subjectedto the second heat-oxidation treatment to form a silicon oxide film 9 ahaving a relatively large thickness on the thick-film portion CK and toform a silicon oxide film 9 b having a relatively small thickness on thethin-film portion IR as shown in FIG. 1(d). The silicon oxide films 9 aand 9 b are used as gate-insulating films of the field-effecttransistor. Then, the gate electrode is formed on the silicon oxidefilms 9 a and 9 b in the same manner as that of forming an ordinaryfield-effect transistor.

[0173] FIGS. 2(a) and 2(b) show the measured results of breakdownvoltage of the silicon oxide film 9 a of when there is employed theprocess for forming two kinds of gate-insulating films of the technicalidea of the invention shown in FIG. 1. For the purpose of comparison,further, FIGS. 3(a), 3(b), 3(c) and 3(d) show the measured results ofbreakdown voltage of the silicon oxide film 52 of when there is employedthe process for forming two kinds of gate-insulating films discussed bythe present inventors shown in FIG. 58. FIGS. 3(a) and 3(b) show theresults of when the silicon oxide film 6 is scraped off by Δdox=1 nm,and FIGS. 3(c) and 3(d) show the results of when Δdox=2 nm. From FIG. 3,it can be said that the silicon oxide film 9 a exhibits better breakdownvoltage when the scraping amount Δdox of the silicon oxide film 6 issmall. For the purpose of comparison, further, FIGS. 4(a) and 4(b) showthe measured results of breakdown voltage of the silicon oxide filmformed by the process for forming one kind of gate-insulating film. InFIGS. 2(a), 3(a), 3(c) and 4(a), the abscissas represent the breakingelectric field intensity of the silicon oxide film formed on thethick-film portion, and the ordinates represent the count of defects. InFIGS. 2(b), 3(b), 3(d) and 4(b), further, the abscissas represent theelectric field intensity of the silicon oxide film formed on thethick-film portion and the ordinates represent the gate current flowingbetween the gate electrode and the semiconductor substrate.

[0174] Here, the polycrystalline silicon film and the tungsten silicidefilm are successively formed on the silicon oxide films 9 a and 52, anda capacitor is so formed by using an exclusive photomask that the areasS of the silicon oxide films 9 a and 52 are 1 cm² each. The siliconoxide film 9 a has a thickness Δdox of, for example, about 8.9 nm andits scraping amount Δdox is, for example, about 1 nm. Further, thesilicon oxide film 52 has a thickness dox of, for example, from about8.2 to 8.3 nm and its scraping amount Δdox is, for example, from about 1to 2 nm. The silicon oxide film formed by the process for forming onekind of gate-insulating film has a thickness dox of, for example, about8.5 nm. As will be understood from FIGS. 2 to 4, by using the technicalidea of the invention, the breakdown voltage of the silicon oxide film 9a can be increased to be nearly equal to that of the silicon oxide filmformed by the process for forming one kind of gate-insulating film. Thatis, when the technical idea of the invention is employed as shown inFIG. 2, the scraping amount Δdox of the thick-film portion can bedecreased (to about 0.2 nm) as compared with the process shown in FIG.58. According to the technical idea of the invention, therefore, it isallowed to suppress or prevent weak spots in the silicon oxide film 6from being exposed during the pre-washing, and the weak spots arefurther suppressed or prevented from expanding into fine pores. Thus,the silicon oxide film 9 a on the thick-film portion maintains improvedquality.

[0175]FIG. 5 is a diagram showing the experimental results obtained bythe inventors, i.e., showing a relationship between the etching amount(equivalent to washing time) in the direction of thickness of thesilicon oxide film on the thin-film portion after the pre-washing (firstwashing SC1) and the thickness of the silicon oxide film left on thesemiconductor substrate. When it is presumed that a silicon oxide filmexists on the thin-film portion, it will be understood from FIG. 5 thatthe above pre-washing must be effected to such a degree as to remove thesilicon oxide film by, for example, not less than 1 nm and, preferably,about 2 nm to improve reliability.

[0176]FIGS. 6 and 7 illustrate the measured results of a relationship(I-V characteristics) between the gate current and the gate voltage ofwhen the silicon oxide film 7 is not left on the silicon oxide film 6(technical idea of the invention) and when the silicon oxide film 7 isleft on the silicon oxide film 6. In FIG. 6 where the silicon oxide film7 is not left on the silicon oxide film 6, there is no change in the I-Vcharacteristics. In FIG. 7 where the silicon oxide film 7 is left on thesilicon oxide film 6, on the other hand, the I-V characteristics undergoa variation, and the field-effect transistor loses the operationstability. It is therefore desired not leave the silicon oxide film 7.

[0177]FIG. 8 illustrates a relationship between the defect density andthe scraping amount of the silicon oxide film on the thick-film portiondue to etching during the pre-washing. Black circles represent points ofmeasuring the defect density of the silicon oxide film on the thick-filmportion formed by the process for forming two kinds of gate-insulatingfilms according to the technical idea of the invention, and an opencircle represents a point of measuring the defect density of the siliconoxide film formed by the process for forming one kind of gate-insulatingfilm. As will be understood from FIG. 8, the process of the inventionmakes it possible to substantially decrease the scraping amount of thesilicon oxide film 6 by etching and, hence, to decrease the defectdensity. According to the study by the inventors, it is desired that thescraping amount is not larger than 1 nm and, preferably, from about 0.2to about 0.5 nm. That is, according to the invention, the scrapingamount of the silicon oxide film on the thick-film portion can bedecreased to be not larger than 1 nm and, hence, to improve reliabilityof the gate-insulating film on the thick-film portion.

[0178]FIG. 9 illustrates a relationship between the count of defects andthe breaking electric field intensity of the silicon oxide film on theside of the thin-film portion when the silicon oxide film is scraped bya thickness of about 1 nm through the pre-washing, wherein FIG. 9(a)illustrates the case of the process for forming one kind ofgate-insulating film and FIG. 9(b) illustrates the case of the processfor forming two kinds of gate-insulating films according to thetechnical idea of the invention. When the technical idea of theinvention is employed concerning the breakdown electric field intensityof the silicon oxide film on the thick-film portion as will beunderstood from FIG. 9, the result becomes comparable to that of whenthe process for forming one kind of gate-insulating film is employed.

[0179]FIGS. 10 and 11 illustrate the measured results of breakdownvoltage of the silicon oxide film 9 a of when the technical idea of theinvention is applied to the so-called salicide process for formingsilicide layers on the gate electrode of the field-effect transistor andon the semiconductor region for source/drain, and the measured resultsof breakdown voltage of the silicon oxide film 52 of when the processfor forming two kinds of gate-insulating films discussed by theinventors is applied to the salicide process. FIGS. 10(a) and 11(a)illustrate only the case where the gate electrode is of the salicidestructure, and FIGS. 10(b) and 11(b) illustrate both the case where thegate electrode is of the salicide structure (triangles representmeasuring points) and the case where the gate electrode is of thepolycide structure (in which a silicide layer is formed on thepolycrystalline silicon film)(circles and squares represent measuringpoints). In the gate electrode of the polycide structure, the silicidelayer is, for example tungsten silicide.

[0180] It will be understood from FIG. 11 that the silicon oxide film 52on the thick-film portion loses the breakdown voltage when the processfor forming two kinds of gate-insulating films discussed by theinventors is adapted to the salicide process or to the polycide process.According to the technical idea of the invention as shown in FIG. 10, onthe other hand, the breakdown voltage of the silicon oxide film 9 a onthe thick-film portion can be improved even when the invention isapplied to the salicide process and to the polycide process. Inparticular, distinguished effect is exhibited when the invention isapplied to the salicide process.

[0181]FIG. 12 illustrates the results of evaluating TDDP (timedependence dielectric breakdown) by measuring the time up to theoccurrence of breakage when the stress of a predetermined electric,field intensity is maintained applied to the gate-insulating film. FIG.12 illustrates a relationship between the cumulative failure and thestressing time (time until failure occurs) for every scraping amountΔdox of the silicon oxide film 6 on the thick-film portion through thepre-washing. Open circles represent a case when Δdox is about 1 nm,triangles represent a case when Δdox is about 0.4 nm, and squaresrepresent a case when Δdox is about 0.2 nm. It will be understood fromFIG. 12 that the stressing time becomes long, i.e., the life becomeslong with a decrease in the scraping amount Δdox.

[0182]FIG. 13 shows the dependence of the final film thickness (siliconoxide film 9 a ) on the thickness of the remaining silicon oxide film 6of when the semiconductor substrate is oxidized in a state where thesilicon oxide film 6 is still remaining on the thick-film portion. Itwill be understood from FIG. 13 that when the semiconductor substrate isoxidized in a state where the silicon oxide film 6 is remaining A, thesilicon oxide film 9 a on the thick-film portion becomes necessarilylarger than the silicon oxide film 9 b on the thin-film portion on thesemiconductor substrate. That is, the region where the silicon oxidefilm 6 is formed first becomes the thick-film portion.

[0183] Next, the method of manufacturing the CMOS according to anembodiment of the invention will be described with reference to FIGS. 14to 26. In the drawings, Qn denotes an n-channel MISFET, Qp denotes ap-channel MISFET, a region A is the one where a thick gate-insulatingfilm will be formed, and a region B is the one where a thingate-insulating film will be formed.

[0184] Referring, first, to FIG. 14, a semiconductor substrate 1constituted by a single silicon crystal having a resistivity of about 10Ω cm is prepared, and a shallow groove 2 is formed in the main surfaceof the semiconductor substrate 1. The depth of the shallow groove 2 is,for example, about 0.35 μm. Then, the semiconductor substrate 1 isheat-oxidized to form a silicon oxide film (not shown). Then, a siliconoxide film 3 is deposited and is polished by a chemical/mechanicalpolishing (CMP) method so that the silicon oxide film 3 is left in theshallow groove 2 only thereby to form an element isolation region(trench isolation).

[0185] In effecting the polishing by the CMP method, variouscontrivances are necessary for preventing the active region from beingpolished and for preventing the surface of the silicon oxide film 3 frombecoming lower than the surface of the active region, which, however,are not described here.

[0186] Next, p-type impurities such as B (boron) ions are injected intothe region where the n-channel MISFET is to be formed thereby to form ap-type well 4, and n-type impurities such as P (phosphorus) ions areinjected into the region where the p-channel MISFET is to be formedthereby to form an n-type well 5.

[0187] Referring next to FIG. 15, the semiconductor substrate 1 isheat-oxidized to form a sacrifice oxide film 20 composed of, forexample, a silicon oxide film on the main surface of the semiconductorsubstrate 1, and the threshold voltages of the n-channel MISFET and ofthe p-channel MISFET are adjusted in a manner as described below.

[0188] First, as shown in FIG. 16, a photoresist pattern 21 a is formedon the main surface of the semiconductor substrate 1 exposing the regionwhere the n-channel MISFET is to be formed but covering other regions.By using the photoresist pattern 21 a as a mask, BF₂ (boron fluoride) isinjected into the channel region of the P-type well 4. Then, thephotoresist pattern 21 a is removed and, as shown in FIG. 17, aphotoresist pattern 21 b is formed on the main surface of thesemiconductor substrate 1 exposing the region where the p-channel MISFETwill be formed but covering other regions. By using the photoresistpattern 21 b as a mask, P (phosphorus) is injected into the channelregion of the n-type well 5. Then, the photoresist pattern 21 b isremoved, and the semiconductor substrate 1 is heat-treated to formthreshold voltage-control layers 22 a and 22 b on the semiconductorsubstrate 1 as shown in FIG. 18. The threshold voltage-control layershave a thickness of, for example, about 20 nm.

[0189] Referring next to FIG. 19, the surface of the semiconductorsubstrate 1 is washed with an aqueous solution containing HF(hydrofluoric acid) and, then, the semiconductor substrate 1 isheat-oxidized to form a silicon oxide film 6 maintaining a thickness ofabout 7 to 8 nm on the surface of the semiconductor substrate 1.

[0190] Referring next to FIG. 20, a silicon oxide film 7 is depositedmaintaining a thickness of about 5 to 15 nm on the silicon oxide film 6which is a protection film by a chemical vapor deposition (CVD) methodof a low pressure at a temperature of about 630° C. The silicon oxidefilm 7 is formed by the thermal decomposition reaction of an organicsource (e.g., si(OC₂H₅)₄). Prior to depositing the silicon oxide film 7,the surface of the silicon oxide film 6 may be washed with an aqueoussolution containing hydrofluoric acid to remove the silicon oxide film 6by about 1 nm. The silicon oxide film 7 may be formed by the CVD methodusing an inorganic source (e.g., SiH₄, SiH₂Cl₂).

[0191] Referring next to FIG. 21, the silicon oxide film 7 and thesilicon oxide film 6 are successively removed from the region B on wherethe thin gate-insulating film is to be formed by using the photoresistpattern 8 as a mask. The photoresist pattern 8 is formed by an ordinaryphotolithography technology. That is, the photoresist pattern 8 isformed by applying a photoresist film and, then, subjecting thephotoresist film to the exposure to light or to the developing.

[0192] Referring next to FIG. 22, the photoresist pattern 8 is removedand, then, the washing is effected for about 5 minutes by using anaqueous solution of, for example, NH₃:H₂O₂:H₂O=2:5:100 maintained at 70°C. Thereafter, the silicon oxide film 7 is chiefly removed with a dilutesolution of hydrofluoric acid. Here, the silicon oxide film 7 formed bythe CVD method is etched at a rate about 15 times as greater as the rateof etching the silicon oxide film 6 formed by the heat oxidation. Thus,the silicon oxide film 7 is selectively removed. The silicon oxide film6 may be removed to such an extent that no defect is introduced into thefilm.

[0193] Referring next to FIG. 23, the semiconductor substrate 1 isheat-oxidized to form a silicon oxide film 9 a having a thickness ofabout 8 nm to constitute a thick gate-insulating film on the region Awhere the silicon oxide film 6 has been formed and to form a siliconoxide film 9 b having a thickness of about 3 to 4 nm to constitute athin gate-insulating film on the region B where the surface of thesemiconductor substrate 1 is being exposed. Here, after the heatoxidation, the oxidizing/nitriding treatment may be effected in an NO orN₂O atmosphere to introduce nitrogen into the silicon oxide films 9 aand 9 b. This improves resistance against the hot carrier effect.

[0194] Referring next to FIG. 24, a polycrystalline silicon film dopedwith n-type impurities such as P is deposited on the semiconductorsubstrate 1 by the CVD method, and the polycrystalline silicon film isetched with the photoresist pattern as a mask thereby to form a gateelectrode 10 constituted by the polycrystalline silicon film.

[0195] Then, with the gate electrode 10 as a mask, n-type impurities(e.g., P) are introduced into the p-type well 4 to form an n⁻-typesemiconductor region 11 a of a low concentration to constitute portionsof source and drain of the n-channel MISFET Qn. Similarly, with the gate10 as a mask, p-type impurities (e.g., BF₂) are introduced into then-type well 5 to form a p⁻-type semiconductor region 12 a of a lowconcentration to constitute portions of source and drain of thep-channel MISFET Qp.

[0196] Referring next to FIG. 25, the silicon oxide film deposited onthe semiconductor substrate 1 by the CVD method is etched by the RIE(reactive ion etching) method in order to form a side wall spacer 13 onthe side wall of the gate electrode 10.

[0197] Next, with the gate electrode 10 and the side wall spacer 13 asmasks, n-type impurities (e.g., As (arsenic)) are introduced into thep-type well 4 to form an n⁺-type semiconductor region 11 b of a highconcentration to constitute other portions of source and drain of then-channel MISFET Qn. Similarly, with the gate electrode 10 and the sidewall spacer 13 as masks, p-type impurities (e.g., BF₂) are introducedinto the n-type well 5 to form a p⁺-type semiconductor region 12 b of ahigh concentration to constitute other portions of source and drain ofthe p-channel MISFET Qp.

[0198] Next, a titanium silicide film 14 of a low resistance is formedon the surface of the gate electrode 10 of the n-channel MISFET Qn, onthe surface of the n³⁰ -type semiconductor region 11 b, on the surfaceof the gate electrode 10 of the p-channel MISFET Qp and on the surfaceof the p⁺-type semiconductor region 12 b by the self-aligning method.That is, a metal film such as of titanium is deposited by the sputteringmethod or the CVD method on the main surface of the semiconductorsubstrate 1 in a state where the upper surfaces of the n⁺-typesemiconductor region 11 b, p⁺-type semiconductor region 12 b and gateelectrode 10 are exposed and, then, the semiconductor substrate 1 isheat-oxidized, in order to form the titanium silicide film 14 on acontact portion between the metal film and the n⁺-type semiconductorregion 11 b, and on a contact portion between the p⁺-type semiconductorregion 12 b and the gate electrode 10. Here, however, the silicide filmthat is formed is in no way limited to the titanium silicide film onlybut may be changed in various ways, and may be, for example, a cobaltsilicide film.

[0199] Referring next to FIG. 26, an interlayer insulating film 15 isformed on the semiconductor substrate 1, a contact hole 16 is perforatedby etching the interlayer insulating film 15, and a wiring layer 17 isformed by etching a metal film (not shown) deposited on the interlayerinsulating film 15 thereby to complete the CMOS device.

[0200] The thickness of the silicon oxide film 7 and the amount ofetching the silicon oxide film 7 play important roles. As required,therefore, the thickness of the film may be managed relying upon amonitor dummy in forming the silicon oxide film 7, and the etchingamount may be regularly managed relying upon the above monitor dummy.

[0201]FIG. 27 is a graph illustrating the measured results of breakdownvoltage of the silicon oxide film 9 a. A capacitor is prepared by usinga special photo mask so as to have an area of the silicon oxide film 9 aof 100 mm² by successively forming a polycrystalline silicon film and atungsten silicide (WSi) film on the silicon oxide film 9 a formed by theproduction steps shown in FIGS. 14 to 23. Here, however, for evaluatingonly the region for forming the n-channel MISFET, the p-type well 4 onlyis formed but the n-type well 5 is not formed. In the upper stage A ofFIG. 27 are shown the breakdown voltages of the laminated films havingthe silicon oxide films 7 of thicknesses of 7.5 nm, 10 nm and 15 nm onthe silicon oxide film 6, and in the lower stage B are shown thebreakdown voltages of when the silicon oxide film 6 is washed prior toforming the silicon oxide film 7. Through the washing, the silicon oxidefilm 6 is removed by about 1 nm.

[0202] Referring to FIG. 27, the silicon oxide film 7 is laminated toprepare a favorable silicon oxide film 9 a having markedly improvedbreakdown voltage. Further, a comparable breakdown voltage is obtainedeven by washing the silicon oxide film 6 prior to forming the siliconoxide film 7. It will be understood that the washing may be effectedafter the silicon oxide film 6 is formed or prior to forming the siliconoxide film 7.

[0203]FIG. 28 illustrates a relationship between the thickness of thesilicon oxide film 7 and the thickness of the silicon oxide film 9 a.Here, the etching is effected after the removal of the photoresistpattern 8 to such an extent that would remove the thickness by about 1nm if it is applied to the silicon oxide film 6.

[0204] After the silicon oxide film 6 is formed maintaining a thicknessof 7 nm, if the semiconductor substrate is heat-oxidized without beingwashed so as to form a silicon oxide film maintaining a thickness of 4nm thereon, then, the thickness of the silicon oxide film 9 a becomes9.1 nm. Therefore, the difference between this value and the thicknessof the silicon oxide film 9 a of when the silicon oxide film 7 is notlaminated, represents the amount by which the silicon oxide film 6 isremoved by etching. When the silicon oxide film 7 is not formed, thesilicon oxide film 9 a has a thickness of 8.1 nm, and a difference of 1nm from the above value of 9.1 nm represents the amount of the siliconoxide film 6 scraped off by washing. Similarly, the scraping amount is0.4 nm when the thickness of the silicon oxide film 7 is 7.5 nm thick,the scraping amount is 0.2 nm when the silicon oxide film 7 is 10 nmthick, and the scraping amount is 0 nm when the silicon oxide film 7 is15 nm thick.

[0205] As shown in FIG. 27, a favorable breakdown voltage is obtainedwhen the silicon oxide film 7 having a thickness of from 7.5 to 10 nm islaminated, from which it will be understood that defect does not almostoccur when the scraping amount Δdox of the silicon oxide film 6 is from0.2 to 0.4 nm. Thus, favorable silicon oxide films 9 a and 9 b areobtained without decreasing the washing amount after the photoresistpattern 8 has been removed.

[0206]FIG. 29 is a plan view of a semiconductor chip 1C in which a DRAM(dynamic random access memory) is formed based on the technical idea ofthe invention. On the main surface of the semiconductor chip 1C isarranged a peripheral circuit area 23 of a crossed shape on a plane soas to equally divide the main surface into four. The four regionsdivided by the peripheral circuit area 23 are memory cell areas 24. Inthis semiconductor chip 1C, the hatched areas represent thick-filmportions on where field-effect transistors are formed having arelatively thick gate-insulating film. The region A of the thick-filmportion occupies a portion of the peripheral circuit area 23 and thememory cell area 24. On the other hand, the region B of the thin-filmportion on which field-effect transistors are formed having a relativelythin gate-insulting film occupies the peripheral circuit area 23 only.In terms of the area, the region A of the thick-film portion is about 30times wider than the region B of the thin-film portion.

[0207] According to this embodiment as described above, the photoresistpattern 8 is not formed directly on the silicon oxide film 6 but isformed thereon via the silicon oxide film 7 which is the protection filmformed by the CVD method at the time of forming two kinds ofgate-insulating films of different thicknesses. Therefore, contaminantsfrom the photoresist film adheres on the silicon oxide film 7 that isformed by the CVD method. Thereafter, the silicon oxide film 7 isselectively removed preventing the silicon oxide film 6 from beingcontaminated by the photoresist film, avoiding the effect of fixedelectric charge in the silicon oxide film 7 and further avoiding damagein the step of removing the resist and in the subsequent step ofwashing. By introducing nitrogen into the silicon oxide films 9 a and 9b, further, the resistance can be increased against the hot carriereffect.

Embodiment 2

[0208] The method of forming the gate-insulating film of the MISFETaccording to another embodiment of the invention will be described withreference to FIGS. 30 to 33.

[0209] First, a threshold voltage control layer is formed in the samemanner as the one described in the embodiment 1 with reference to FIGS.16 to 18.

[0210] Referring next to FIG. 30, the surface of the semiconductorsubstrate 1 is washed with an aqueous solution of hydrofluoric acid and,then, a silicon oxide film 6 a is deposited by the CVD method. Informing the silicon oxide film 6 a, another silicon oxide film may bedeposited maintaining a thickness of about 1 nm as an underlying film toprevent the infiltration of contaminant into the semiconductor substrate1 or to maintain favorable interface properties between the siliconoxide film 6 a and the semiconductor substrate 1. As a method ofdepositing the underlying film, piece-by-piece oxidation may be effectedat a low temperature of about 700° C. for short periods of time prior todepositing the silicon oxide film 6 a, or the sequence for forming thesilicon oxide film 6 a may be so changed as to start depositing thesilicon oxide film 6 a after being left to stand in a high-temperatureoxidizing atmosphere. Thereafter, a silicon oxide film 7 a is formed bythe CVD method on the silicon oxide film 6 a, the silicon oxide film 7 aserving as a protection film and having a composition different from thesilicon oxide film 6 a.

[0211] Referring next to FIG. 31, the silicon oxide film 7 a and thesilicon oxide film 6 a are successively removed from the region B onwhere a thin gate-insulating film is to be formed by using thephotoresist pattern 8 as a mask.

[0212] Referring next to FIG. 32, the photoresist pattern 8 is removedand, then, the silicon oxide film 7 a is chiefly removed. Referring nextto FIG. 33, a silicon oxide film 9 c is deposited on the semiconductorsubstrate 1 by the CVD method. Prior to depositing the silicon oxidefilm 9 c, a silicon oxide film may be deposited maintaining a thicknessof about 1 nm as an underlying film on the exposed surface of thesemiconductor substrate 1. Thus, a laminate of the silicon oxide film 6a and the silicon oxide film 9 c is formed on the region A where thethick gate-insulating film is to be formed, and the silicon oxide film 9c only is formed on the region B where the thin gate-insulting film isto be formed.

Embodiment 3

[0213] The method of forming the gate-insulating film of the MISFETaccording to a further embodiment of the invention will be described.

[0214] In this embodiment 3, first, the silicon oxide film 6 is providedon the region A where the thick gate-insulating film is to be formed asshown in FIG. 22 by the method described in the embodiment 1 exposingthe surface of the region B of the semiconductor substrate 1 on wherethe thin gate-insulating film is to be formed.

[0215] Thereafter, an insulating film other than the silicon oxide film,such as a film of silicon nitride (SiN), a film of tantalum oxide(Ta₂O₅) or a film of titanium oxide (TiO₂) is formed on thesemiconductor substrate 1. These films can be deposited by the CVDmethod, plasma CVD method or JVD (jet vapor deposition) method. Prior todepositing the insulating film, a silicon oxide film may be depositedmaintaining a thickness of about 1 nm as an underlying film on theexposed surface of the semiconductor substrate 1. Thus, a laminate ofthe silicon oxide film 6 and the insulating film is formed on the regionA where the thick gate-insulating film is to be formed and the aboveinsulating film only is formed on the region B where the thingate-insulating film is to be formed.

[0216] That is, part of the gate-insulating film on the region A whichis the thick-film portion and the whole gate-insulating film on theregion B which is the thin-film portion are formed of a material havinga dielectric constant larger than that of the silicon oxide film inorder to increase the thickness of the gate-insulating films compared towhen the gate-insulating films are formed of the silicon oxide film onlyyet maintaining comparable characteristics of the MISFET. This makes iteasy to form the gate-insulating films. It is further allowed tosuppress or prevent the flow of a gate current (tunnel current) betweenthe gate electrode and the-semiconductor substrate.

Embodiment 4

[0217] Described below is a method of forming the gate-insulating filmof the MISFET according to a still further embodiment of the invention.

[0218] In this embodiment 4, first, the silicon oxide film 6 a isprovided on the region A where the thick gate-insulating film is to beformed as shown in FIG. 32 by the method described in the embodiment 2exposing the surface of the region B of the semiconductor substrate 1 onwhere the thin gate-insulating film is to be formed.

[0219] Thereafter, an insulating film other than the silicon oxide film,such as a film of SiN, a film of Ta₂O₅ or a film of TiO₂ is formed onthe semiconductor substrate 1. These films can be deposited by the CVDmethod, plasma CVD method or JVD method. Prior to depositing theinsulating film, a silicon oxide film may be deposited maintaining athickness of about 1 nm as an underlying film on the exposed surface ofthe semiconductor substrate 1. Thus, a laminate of the silicon oxidefilm 6 a and the above insulating film is formed on the region A wherethe thick gate-insulating film is to be formed and the above insulatingfilm only is formed on the region B where the thin gate-insulating filmis to be formed. Therefore, the following effects are obtained like inthe above embodiment 3. This makes it easy to form the gate-insulatingfilms. It is further allowed to suppress or prevent the flow of a gatecurrent (tunnel current) between the gate electrode and thesemiconductor substrate.

Embodiment 5

[0220] Described below is a method of forming the gate-insulating filmof the MISFET according to a yet further embodiment of the invention.

[0221] In this embodiment 5, first, a laminate of the silicon oxide film6 a and the silicon oxide film 9 c is formed on the region A where thethick gate-insulating film is to be formed, and the silicon oxide film 9c only is formed on the region B where the thin gate-insulating film isto be formed as shown in FIG. 33 by the method described in theembodiment 2.

[0222] Thereafter, the semiconductor substrate 1 is subjected to theheat-nitriding, plasma-nitriding or radical-nitriding in order toimprove properties on the interface between the silicon oxide film 6 aand the semiconductor substrate 1 and between the silicon oxide film 9 cand the semiconductor substrate 1.

Embodiment 6

[0223] Described below is a method of forming the gate-insulating filmof the MISFET according to a further embodiment of the invention.

[0224] In this embodiment 6, first, the surface of the semiconductorsubstrate 1 is washed with an aqueous solution of hydrofluoric acid asshown in FIG. 30 by the method described in the embodiment 2, and asilicon oxide film 6 a is deposited by the CVD method. In forming thesilicon oxide film 6 a, another silicon oxide film may be depositedmaintaining a thickness of about 1 nm as an underlying film in order toprevent the infiltration of contaminants into the semiconductorsubstrate 1 or to maintain favorable interfacial properties between thesilicon oxide film 6 a and the semiconductor substrate 1.

[0225] Next, the semiconductor substrate 1 is subjected to theheat-nitriding, plasma-nitriding or radical-nitriding to reform part ofthe silicon oxide film 6 a.

[0226] Thereafter, a laminate of the reformed film of the silicon oxidefilm 6 a and the silicon oxide film 9 c is formed on the region A wherethe thick gate-insulating film is to be formed and the silicon oxidefilm 9 c only is formed on the region B where the thin gate-insulatingfilm is to be formed in the same manner as the one described inembodiment 2.

[0227]FIG. 34 illustrates a device used for reforming (plasma-nitridingor radical-nitriding) the silicon oxide film 6 a. FIG. 34 shows an RPN(remote plasma nitriding) device 25. A nitrogen gas introduced into thedevice is converted into a plasma thereof through a plasma-generatingunit 25 a, and is fed onto the main surface of the semiconductorsubstrate 1 (semiconductor wafer) placed on a wafer stage 25 b. Then,nitrogen radicals react with the insulating film (silicon oxide film 6a, etc) on the main surface of the semiconductor substrate to form anitride film (nitride layer). FIG. 35 shows a profile of nitrogen in thefilm subjected to the RPN treatment by the SIMS (secondary ion massspectrometry=secondary ion mass analysis)(R. Kraft, T. P. Schneider, W.W. Dostalik and S. Hattangady, J. Vac. Sci. Technol. B15(4), p. 967,July/August, 1997). For the purpose of comparison, FIG. 36 shows an SIMSprofile of the nitride film using the nitrogen oxide (NO) gas. It willbe understood from FIGS. 35 and 36 that when the RPN treatment iseffected, the profiles of oxygen and nitrogen are reversed compared tothe nitride film using NO, and nitrogen is distributed on the surfaceside. When this method is employed, a very thin nitride film can beeasily formed. Further, since nitrogen and silicon oxide can be firmlybonded together, resistance is improved against the etching.

Embodiment 7

[0228] A method of forming the gate-insulating film of the MISFETaccording to another embodiment of the invention will be described withreference to FIGS. 37 to 40.

[0229] First, the threshold voltage control layer is formed in the samemanner as in the embodiment 1 described with reference to FIGS. 16 to18.

[0230] Referring next to FIG. 37, the surface of the semiconductorsubstrate 1 is washed with an aqueous solution of hydrofluoric acid.Then, a silicon oxide film 6 is formed on the surface of thesemiconductor substrate 1, and a silicon oxide film 7 is deposited as aprotection film on the silicon oxide film 6 by the CVD method.

[0231] Referring next to FIG. 38, the silicon oxide film 7 on the regionB where the thin gate-insulating film is formed is chiefly etched with abufferred hydrofluoric acid solution using the photoresist pattern 8 asa mask.

[0232] Next, impurities 18 for controlling the threshold voltage of theMISFET are injected into the semiconductor substrate 1 to form a channellayer 19. Here, the impurities 18 are injected in the same manner asthose injected into the region where the n-channel MISFET is formed andthose injected into the region where the p-channel MISFET is formed onthe region B of forming the thin gate-insulating film. Therefore, theseimpurities play the role of counter-injection against the impuritiesinjected for forming the threshold voltage control layer explained withreference to FIGS. 16 to 18.

[0233] Then, the silicon oxide 6 that had not been removed by the aboveetching is removed by using the bufferred hydrofluoric acid solution.

[0234] Referring next to FIG. 39, the photoresist pattern 8 is removedfollowed by washing for about 5 minutes by using an aqueous solution of,for example, NH₃:H₂O₂:H₂O=2:5:100 heated at 70° C. Then, the siliconoxide film 7 is chiefly removed with a solution of hydrofluoric acid.

[0235] Referring next to FIG. 40, the semiconductor substrate 1 isheat-oxidized to form a silicon oxide film 9 a for constituting a thickgate-insulating film on the region A on where the silicon oxide film 6has been formed, and to form a silicon oxide film 9 b for constituting athin gate-insulating film on the region B on where the surface of thesemiconductor substrate 1 is being exposed.

[0236] Instead of forming the silicon oxide films 9 a and 9 b, there maybe deposited a film of silicon oxide, a film of SiN, a film of Ta₂O₅ ora film of TiO₂ on the semiconductor substrate 1 by the CVD method. Priorto depositing these insulating films, further, the silicon oxide filmmay be deposited maintaining a thickness of about 1 nm as an underlyingfilm by the heat treatment on the exposed surface of the semiconductorsubstrate 1.

Embodiment 8

[0237] Described below with reference to FIGS. 41 to 44 is the method offorming the gate-insulating film of the MISFET according to anotherembodiment of the invention.

[0238] First, the threshold voltage control layer is formed by the samemethod as the one explained in the embodiment 1 with reference to FIGS.16 to 18.

[0239] Referring next to FIG. 41, the surface of the semiconductorsubstrate 1 is washed with an aqueous solution of hydrofluoric acid and,then, a silicon oxide film 6 a is deposited by the CVD method. Informing the silicon oxide film 6 a, another silicon oxide film may bedeposited maintaining a thickness of about 1 nm as an underlying film inorder to prevent the infiltration of contamination into thesemiconductor substrate 1 or to maintain favorable interfacialproperties between the silicon oxide film. 6 a and the semiconductorsubstrate 1. Thereafter, a silicon oxide film 7 a is deposited by theCVD method on the silicon oxide film 6 a, the silicon oxide film 7 aserving as a protection film and having a composition different from thesilicon oxide film 6 a.

[0240] Referring next to FIG. 42, the silicon oxide film 7 a only isremoved by etching from the region B on where a thin gate-insulatingfilm is to be formed using the photoresist pattern 8 as a mask.

[0241] Next, impurities 18 for controlling the threshold voltage of theMISFET are injected into the semiconductor substrate 1 to form a channellayer 19. Here, the impurities 18 are injected in the same manner asthose injected into the region where the n-channel MISFET is formed andthose injected into the region where the p-channel MISFET is formed onthe region B of forming the thin gate-insulating film. Therefore, theseimpurities play the role of counter-injection against the impuritiesinjected for forming the threshold voltage control layer explained withreference to FIG. 1.

[0242] Then, the silicon oxide 6 a that had not been removed by theabove etching is removed by using the bufferred hydrofluoric acidsolution.

[0243] Referring next to FIG. 43, the photoresist pattern 8 is removedfollowed by washing for about 5 minutes by using an aqueous solution of,for example, NH₃:H₂O₂:H₂O=2:5:100 heated at 70° C. Then, the siliconoxide film 7 a is chiefly removed with a solution of hydrofluoric acid.

[0244] Referring next to FIG. 44, an insulating film such as a film ofSiN, a film of Ta₂O₅ or a film of TiO₂ is deposited on the semiconductorsubstrate 1 by the CVD method. Prior to depositing these insulatingfilms, further, the silicon oxide film may be deposited maintaining athickness of about 1 nm as an underlying film by heat-treating theexposed surface of the semiconductor substrate 1. Thus, a laminate ofthe silicon oxide film 6 a and the above insulating film is formed onthe region A where the thick gate-insulating film is to be formed andthe above insulating film only is formed on the region B where the thingate-insulating film is to be formed. Therefore, the following effectsare obtained like in the above embodiment 4. This makes it easy to formthe gate-insulating films. It is further allowed to suppress or preventthe flow of a gate current (tunnel current) between the gate electrodeand the semiconductor substrate.

Embodiment 9

[0245] A further technical idea of the invention will be described nextwith reference to FIGS. 45(a) to 45(d).

[0246] First, as shown in FIG. 45(a), the semiconductor substrate 1 isheat-oxidized to form a silicon oxide film 6 on the main surface (activeregion) of the semiconductor substrate 1. Then, an insulating film 26 isdeposited as a protection film on the silicon oxide film 6 in a mannerof being directly contacted thereto. The insulating film 26 has ananti-oxidizing property and is not almost etched through the pre-washing(e.g., washing with hydrofluoric acid). Besides, the insulting film 26is formed having a thickness smaller than that of the silicon oxide film6.

[0247] Next, a photoresist pattern 8 is formed being directly contactedto the insulating film 26 covering the thick-film portion but exposingthe thin-film portion. Then, the insulating film 26 and the siliconoxide film 6 are successively removed from the thin-film portion usingthe photoresist pattern 8 as an etching mask.

[0248] Thereafter, the photoresist pattern 8 is removed by ashing toobtain a sectional structure shown in FIG. 45(b). Here, since theinsulating film 26 has been formed on the silicon oxide film 6 under thephotoresist pattern 8, the silicon oxide film 6 is damaged little.

[0249] Next, the back surface of the semiconductor substrate 1 iswashed. The washing of back surface includes, for example, a firstwashing and a second washing as described in the embodiment 1 above.

[0250] Then, the whole semiconductor substrate 1 inclusive of the mainsurface is subjected to the pre-washing in the same manner as in theprocess for forming two kinds of gate-insulating films studied by thepresent inventors as described above. FIG. 45(c) is a sectional viewillustrating a major portion of the semiconductor substrate 1 after thepre-washing, wherein Δdt represents the amount by which the insulatingfilm 26 is scraped. This eliminates the spontaneously oxidized filmformed on the main surface of, for example, the thin-film portion of thesemiconductor substrate 1 and to decrease or eliminate damage at thetime of removing the photoresist film.

[0251] According to the technical idea of the invention, the insulatingfilm 26 is not almost etched through the pre-washing (e.g., washing withhydrofluoric acid). This prevents weak spots in the silicon oxide film 6from being exposed during the pre-washing, making it possible to securethe breakdown voltage of the gate-insulating film on the thick-filmportion where a high breakdown voltage is required. The insulating film26 works as a stopper during the pre-washing and, hence, the siliconoxide film 6 remains. This contributes to improving precision forsetting the thickness of the silicon oxide film 6.

[0252] According to the technical idea of the invention, too, thesilicon oxide film 6 on the thick-film portion is covered with theinsulating film 26 which is the protection film and does not come intodirect contact with the photoresist pattern 8 like in the aboveembodiment 1, making it possible to decrease or prevent the siliconoxide film 6 from being contaminated by the photoresist film. Like inthe above embodiment 1, therefore, much attention needs not be given tothe contamination of the silicon oxide film 6 by the photoresist filmduring the pre-washing.

[0253] After the pre-washing, the semiconductor substrate 1 is subjectedto the second heat oxidation to form a silicon oxide film 9 b thatconstitutes a relatively thin gate-insulating film on the thin-filmportion as shown in FIG. 45(d). Here, no film is formed since theinsulating film 26 having anti-oxidizing property has been formed on thethick-film portion. Therefore, the relatively thick gate-insulating filmon the thick-film portion is constituted by the silicon oxide film 6 andby the insulating film 26 formed thereon. Thereafter, a gate electrodeis formed on the insulating film 26 and on the silicon oxide film 9 b inthe same manner as that of forming an ordinary field-effect transistor.Thus, the technical idea of the invention described above offers thesame effect as that of the invention described in the above embodiment1.

[0254] Next, described below is the case where the technical idea of theinvention is applied to a method of manufacturing a semiconductorintegrated circuit device having, for example, a CMIS (complementarymetal insulator semiconductor) circuit.

[0255] First, after the steps same as the steps of manufacturing thesemiconductor integrated circuit device explained with reference toFIGS. 14 to 19 of embodiment 1, an insulating film 26 is formed as aprotection film on the silicon oxide film 6 as shown in FIG. 46. Theinsulating film 26 is composed of a material having anti-oxidizingproperty and resistance against the washing, and is, for example, asilicon nitride film. The insulating film 26 has a thickness smallerthan that of the silicon oxide film 6 a, i.e., has a thickness of, forexample, from about 0.5 to about 1.0 μm that is not removed through thepre-washing that will be described later. The insulating film 26 isformed by, for example, depositing an insulating film of silicon nitrideon the silicon oxide film by the CVD method or JVD method, or byreforming the surface of the silicon oxide film 6 by the PRN treatmentsuch as plasma-nitriding or radical-nitriding, or by the heat-nitriding.In the case of the reforming (particularly, when the PRN treatment isemployed), a very thin insulating film 26 can be formed maintaining ahigh precision. Further, the insulating film 26 is formed in a statewhere nitrogen and the silicon oxide film are bonded together, featuringhighly bonded state and large resistance against the etching.

[0256] Referring next to FIG. 47, a photoresist pattern 8 same as thatof the embodiment 1 is formed on the insulating film 26 and is used asan etching mask to successively etch the insulating film 26 and thesilicon oxide film 6 from the region B which is the thin-film portion.Thereafter, the photoresist pattern 8 is removed followed by the samepre-washing as that of the embodiment 1 to obtain a structure shown inFIG. 48. The insulating film 26 is not almost etched through thepre-washing. Therefore, the silicon oxide film 6 and the insulating film26 are left on the region A which is the thick-film portion.

[0257] Next, the semiconductor substrate 1 is heat-oxidized to form asilicon oxide film 9 b on the main surface of the region B which is thethin-film portion of the semiconductor substrate 1 as shown in FIG. 49.No film is formed on the region A which is the thick-film portion sincethe insulating film 26 having a strong anti-oxidizing property has beenformed thereon, and a laminate of the silicon oxide film 6 and theinsulating film 26 is formed thereon. Referring next to FIG. 50, gateelectrodes 10 are formed on the silicon oxide film 9 b and on theinsulating film 26 in the same manner as in the embodiment 1. Thesubsequent steps are the same as those of the embodiment 1 and are notdescribed. In this embodiment 9, too, the insulating film 26 of siliconnitride is formed on the gate-insulating film on the region A which isthe thick-film portion, exhibiting the following effects like thoseobtained in the above embodiment 4. This makes it easy to form thegate-insulating film on the thick-film portion. It is further allowed tosuppress or prevent the flow of a gate current (tunnel current) betweenthe gate electrode and the semiconductor substrate in the thick-filmportion of the MISFET.

Embodiment 10

[0258] The embodiment 10 is a modification from the embodiment 9.

[0259] First, after the steps of FIGS. 46 to 48, an insulating film 27having a high dielectric constant is formed on the semiconductorsubstrate 1 as shown in FIG. 51. Thus, a gate-insulating film which isan insulating film 27 is formed on the region B which is the thin-filmportion, and a gate-insulating film which is a laminate of theinsulating film 27 formed on the silicon oxide film 6 via the insulatingfilm 26, is formed on the region A which is the thick-film portion. Theinsulating film 27 is, for example, the one of silicon nitride formed bythe CVD method, RPN method or JVD method like the insulating film 26, oris the one of tantalum oxide (Ta_(x)O_(y): e.g., Ta₂O₅), titanium oxide(TiO_(x): e.g., TiO₂) or SiON. The insulating film 27 hay have athickness required for the gate-insulating film on the region B which isthe thin-film portion. In this embodiment 10, the insulating film 27 hasa high dielectric constant. Therefore, despite the thickness is not sosmall, the MISFET exhibits performance comparable to that of when thesilicon oxide film 9 b (see FIG. 49) has a small thickness. It istherefore allowed to form the gate-insulating films maintainingrelatively large thicknesses on the region A which is the thick-filmportion and on the region B which is the thin-film portion, enabling thefilm thicknesses to be easily controlled like in the embodiment 4. It isfurther allowed to suppress or prevent the leakage current between thegate electrode and the semiconductor substrate. Then, as shown in FIG.52, gate electrodes 10 are formed on the insulating film 27 on theregion A which is the thick-film portion and on the region B which isthe thin-film portion like in the embodiment 1. The subsequent steps arethe same as those of the embodiment 1 and are not described.

Embodiment 11

[0260] The embodiment 11 deals with a modification of the gateelectrodes of the MISFET, i.e., deals with a method of forming aso-called dual gate-polymetal gate electrode structure, and can beapplied to any one of the embodiments 1 to 10.

[0261] First, after the steps same as those of the embodiment 1 shown inFIGS. 14 to 23, a polycrystalline silicon film 28 is deposited by theCVD method on the main surface of the semiconductor substrate 1 as shownin FIG. 53. Referring next to FIG. 54, a photoresist pattern 29 is soformed on the polycrystalline silicon film 28 as to expose the regionwhere the n-channel MISFET is to be formed but to cover other regions.By using the photoresist pattern 29 as a mask, impurities such as P(phosphorus) ions are injected into a portion of the polycrystallinesilicon film 28 that is not covered by the photoresist pattern 29. Thus,the portion of the polycrystalline silicon film 28 on the p-type well 4assumes the n⁻-type. Then, after the photoresist pattern 29 is removed,a photoresist pattern 30 is formed on the polycrystalline silicon film28 permitting the p-channel MISFET-forming region to be exposed butcovering other regions as shown in FIG. 55. Then, by using thephotoresist pattern 30 as a mask, impurities such as B (boron) ions areinjected into a portion of the polycrystalline silicon film 28 that isnot covered by the photoresist pattern 30. Thus, the portion of thepolycrystalline silicon film 28 on the n-type well assumes the p⁺-type.

[0262] Referring next to FIG. 56, an electrically conducting film 31such as of tungsten nitride or titanium nitride is deposited bysputtering on the polycrstalline silicon film 28 and, then, as shown inFIG. 57, an electrically conducting film 32 of ,tungsten or the like isdeposited thereon by sputtering. Further, an insulating film 33 for acap comprising, for example, a silicon oxide film or a silicon nitridefilm is deposited thereon by the CVD method. The electrically conductingfilm 31 suppresses the formation of a silicide layer that results fromthe reaction of tungsten in the electrically conducting film 32 withsilicon in the polycrystalline silicon film 28. Then, thepolycrystalline silicon film 28, the electrically conducting films 31and 32 and the insulating film 33 for cap are patterned by thephotolithography technology and dry-etching technology, in order to formthe gate electrode 10 and the insulating film 33 for cap thereon in thesame manner as in the embodiment 1. The subsequent steps are the same asthose of the embodiment 1 and are not described.

[0263] This embodiment 11, too, exhibits the same effect as that of theembodiments 1 to 10. In particular, the following effect is obtainedwhen the gate electrode structure of this embodiment 11 is applied tothe above embodiments 5, 9 and 10. That is, in the embodiment 5, thenitride film (nitride layer) is formed on the gate-insulating films ofMISFETs in the thick-film portion and in the thin-film portion. In theembodiments 9 and 10, further, the gate-insulating film of the MISFET onthe thick-film portion is constituted by a laminate of the silicon oxidefilm 6 on which are deposited insulating films 26 and 27 of siliconnitride (see FIGS. 50 and 52). Accordingly, the nitride layers or theinsulating films 26 and 27 suppress or prevent boron ions having a highdiffusion coefficient in the gate electrodes 10 from being diffused tothe side of the silicon oxide film. This makes it possible to improveoperation reliability and yield of the p-channel MISFETs.

[0264] In the foregoing was concretely described the inventionaccomplished by the present inventors by way of embodiments. It should,however, be noted that the invention is in no way limited to theabove-mentioned embodiments only but can be modified in a variety ofother ways without departing from the gist and scope of the invention.

[0265] The above embodiments 1 to 11 have dealt with the case where theinvention was adapted to the semiconductor integrated circuit devicehaving, for example, a CMIS circuit and to the DRAM. Not being limitedthereto only, however, the invention can be adapted to a semiconductordevice having a memory circuit, such as SRAM (static random accessmemory) or flush memory (EEPROM: electric erasable programmableread-only memory), to a semiconductor device having a logic circuit,such as microprocessor, and to a hybrid semiconductor device having thememory circuit and the logic circuit formed in the same semiconductorsubstrate.

[0266] Briefly described below are effects obtained by representativeexamples of the invention disclosed in this application.

[0267] According to the invention, a plurality of kinds ofgate-insulating films having dissimilar thicknesses are formed withoutcausing contamination from the resist film, avoiding damage in the stepof removing the resist and in the subsequent step of washing and, hence,without deteriorating the breakdown voltage of the gate-insulatingfilms. Further, the interface level is lowered to stabilize theoperation characteristics of the MISFET, contributing to improvingreliability of the MISFET having a plurality of kinds of gate-insulatingfilms of dissimilar thicknesses.

[0268] According to the invention, further, the thicknesses of thegate-insulating films are favorably controlled, and the productionyields of MISFETs can be enhanced.

What is claimed is:
 1. A method of manufacturing a semiconductorintegrated circuit device, comprising the steps of: (a) forming a firstinsulating film on the surface of a semiconductor substrate having afirst active region and a second active region; (b) forming a protectionfilm on said first insulating film; (c) successively removing saidprotection film and said first insulating film from said second activeregion; (d) cleaning said semiconductor substrate after said step (c);and (e) forming a second insulating film on said semiconductor substrateafter said step (d) to form an insulating film of a first relativelylarge thickness on said first active region and to form an insulatingfilm of a second relatively small thickness on said second activeregion, wherein said protective film is removed from said first activeregion in said step (d).
 2. A method of manufacturing a semiconductorintegrated circuit device according to claim 1, wherein in effectingsaid cleaning in said step (d), the rate for etching said protectionfilm is larger than the rate for etching said first insulating film, andsaid second insulating film is removed from said second active region.3. A method of manufacturing a semiconductor integrated circuit deviceaccording to claim 1, wherein the amount of reduction of the thicknessof said first insulating film in said step (d) is not more than 1 nm. 4.A method of manufacturing a semiconductor integrated circuit deviceaccording to claim 3, wherein the amount of reduction of the thicknessof said first insulating film in said step (d) is from 0.2 to 0.4 nm. 5.A method of manufacturing a semiconductor integrated circuit deviceaccording to claim 1, wherein said second insulating film is formed by achemical vapor-phase deposition method.
 6. A method of manufacturing asemiconductor integrated circuit device according to claim 1, whereinthe insulating film having said first thickness and the insulating filmhaving said second thickness work as gate-insulating films of theMISFET.
 7. A method of manufacturing a semiconductor integrated circuitdevice according to claim 1, wherein in said step of cleaning, saidprotection film works to suppress the scraping of said first insulatingfilm.
 8. A method of manufacturing a semiconductor integrated circuitdevice according to claim 1, wherein said protection film is formed bythe chemical vapor-phase deposition method.
 9. A method of manufacturinga semiconductor integrated circuit device according to claim 1, whereinsaid second insulating film has a dielectric constant larger than thatof said first insulating film.
 10. A method of manufacturing asemiconductor integrated circuit device according to claim 1, whereinsaid first insulating film is formed by a chemical vapor-phasedeposition method.
 11. A method of manufacturing a semiconductorintegrated circuit device according to claim 1, wherein said firstinsulating film is formed by a thermal oxidation method in said step(a), wherein said second insulating film is formed by a thermaloxidation method in said step (e), and wherein said protection film isformed by a chemical vapor-phase deposition method in said step (b). 12.A method of manufacturing a semiconductor integrated circuit device,comprising steps of: (a) forming a first insulating film on a mainsurface of a semiconductor substrate having a first active region and asecond active region; (b) forming a protection film on said firstinsulating film; (c) covering said first active region with a maskingpattern; (d) removing said protection film and said first insulatingfilm from said second active region by using said masking pattern as amask; (e) after said step (d), cleaning said semiconductor substrate;and (f) after said step (e), forming a second insulating film, on saidsecond active region, having a film thickness thinner than that of saidfirst insulating film, wherein in said step (e) a rate for etching saidprotection film is larger than a rate for etching said first insulatingfilm such that said protection film is removed from said second activeregion, wherein said first insulating film serves as a gate insulatingfilm of a first MISFET formed on said first active region, and whereinsaid second insulating film serves as a gate insulating film of a secondMISFET formed on said second active region.
 13. a method ofmanufacturing a semiconductor integrated circuit device according toclaim 12, wherein in said step (e) an amount of reduction of a thicknessof said first insulating film is not more than 1 nm.
 14. A method ofmanufacturing a semiconductor integrated circuit device according toclaim 12, wherein in said step of cleaning, said protection film worksto suppress the scraping of said first insulating film.
 15. A method ofmanufacturing a semiconductor integrated circuit device according toclaim 12, wherein said second insulating film has a dielectric constantlarger than that of said first insulating film.
 16. A method ofmanufacturing a semiconductor integrated circuit device according toclaim 12, wherein said second insulating film is formed by a chemicalvapor-phase deposition method.
 17. A method of manufacturing asemiconductor integrated circuit device according to claim 12, whereinsaid first insulating film is formed by a chemical vapor-phasedeposition method.
 18. A method of manufacturing a semiconductorintegrated circuit device according to claim 12, wherein said firstinsulating film is formed by a thermal oxidation method in said step(a), wherein said second insulating film is formed by a thermaloxidation method in said step (f), and wherein said protection film isformed by a chemical vapor-phase deposition method in said step (b). 19.A method of manufacturing a semiconductor integrated circuit devicecomprising steps of: (a) forming a first insulating film on a mainsurface of a semiconductor substrate having a first active region and asecond active region; (b) forming a protection film on said firstinsulating film; (c) selectively removing said protection film and saidfirst insulating film from said second active region, (d) after saidstep (c), cleaning said semiconductor substrate; and (e) after said step(d), forming a second insulating film, on said second active region,having a film thickness thinner than that of said first insulating film,wherein in said step (d) a rate for etching said protection film islarger than a rate for etching said first insulating film such that saidprotection film is removed from said second active region, wherein saidfirst insulating film serves as a gate insulating film of a first MISFETformed on said first active region, and wherein said second insulatingfilm serves as a gate insulating film of a second MISFET formed on saidsecond active region.
 20. A method of manufacturing a semiconductorintegrated circuit device according to claim 19, wherein in said step(e) an amount of reduction of a thickness of said first insulating filmis not more than 1 nm.
 21. A method of manufacturing a semiconductorintegrated circuit device according to claim 19, wherein said firstinsulating film is formed by a thermal oxidation method in said step(a), wherein said second insulating film is formed by a thermaloxidation method in said step (e), and wherein said protection film isformed by a chemical vapor-phase deposition method in said step (b). 22.A method of manufacturing a semiconductor integrated circuit device,comprising steps of: (a) forming a first insulating film on a mainsurface of a semiconductor substrate having a first active region and asecond active region; (b) forming a protection film on said firstinsulating film; (c) selectively removing said protection film and saidfirst insulating film from said second active region; (d) after saidstep (c), cleaning said semiconductor substrate such that saidprotection film is removed from said second active region; and (e) aftersaid step (d), forming a second insulating film, on said second activeregion, having a film thickness thinner than that of said firstinsulating film, wherein said first insulating film serves as a gateinsulating film of a first MISFET formed on said first active region,and wherein said second insulating film serves as a gate insulating filmof a second MISFET formed on said second active region.
 23. A method ofmanufacturing a semiconductor integrated circuit device according toclaim 22, wherein said first insulating film is formed by a thermaloxidation method in said step (a), wherein said second insulating filmis formed by a thermal oxidation method in said step (e), and whereinsaid protection film is formed by a chemical vapor-phase depositionmethod in said step (b).
 24. A method of manufacturing a semiconductorintegrated circuit device according to claim 22, wherein said secondinsulating film has a dielectric constant larger than that of said firstinsulating film.
 25. A method of manufacturing a semiconductorintegrated circuit device according to claim 22, wherein in said step(d) an amount of reduction of a thickness of said first insulating filmis not more than 1 nm.